This invention relates to integrated circuit carriers, and more particularly to functional glass handler wafer with through vias.
In the packaging of semiconductor chips, typically an organic laminate substrate is used which fans out the fine pitch, typically 0.15 to 0.2 mm, C4 solder bumps on the silicon die to larger pitch, typically 1.0 to 1.2 mm, BGA (ball grid array) or LGA (land grid array) connections. With a BGA, the chip package is attached to a printed circuit board by reflowing the solder balls to form a permanent connection whereas an LGA type interposer provides a connection where the chip package can be readily removed and replaced on the printed circuit board (PCB). The pitch of the C4s limits the amount of input/output signals, i.e., I/O which can be provided to a chip. Note that a significant fraction of the C4s is typically required for power delivery. The minimum C4 pitch between a chip and the package substrate to which it is attached is a function of the chip size and the difference in the thermal coefficient of expansion (TCE) between the chip and the substrate. Thermal cycling results in stresses at the C4 connections between the chip and substrate if the TCE is different. Larger pitch C4s, which are also taller, can relieve a greater strain before failing.
One recently developed approach to increasing the I/O off of a chip is to use a silicon carrier, or interposer, which is placed between the chip and the laminate substrate and provides a space transform between fine pitch microbump connections to the chip with larger pitch C4 connections to the laminate substrate. Since both the chip and carrier are made of silicon, fine pitch microbumps can be used since there is no difference in TCE.
The use and assembly of a conventional silicon carrier may include bonding the silicon wafer using a polymer layer to a glass handler wafer. After dicing, the silicon carrier is then placed on a packaging substrate, which is typically an organic laminate but can also be a multilayer ceramic, such that the C4s are aligned with corresponding pads, and reflowed to form electrical connections through the C4s. The glass handler wafer portion is then removed, typically with a laser release process which ablates/vaporizes the polymer adhesive between the silicon carrier and the glass handler. After appropriate cleaning and surface treatments, the chip or chips are then connected to the silicon carrier using microbumps and an underfill material is applied to both the C4 and the microbump layers and cured. Alternate assembly sequences such as underfilling the Si carrier prior to attaching the chips with microbumps are also possible.